About icoBoard

Enabling open source FPGA solutions

icoBOARD is a FPGA based IO board for RaspberryPi. The icoBOARD contains a Lattice FPGA (Field Programmable Gate Array) with 8k LUT, 100MHz max clock, up to 8 MBit of SRAM and is programmable in Verilog (A hardware description language) by a complete open source FPGA toolchain.icoboard-vorne-1-1

The icoTC (toolchain consisting of Yosys and ArachnePnR and icetools) for the Lattice ICE40 series supports all chip components like PLLs, Block RAMs, the WARMBOOT macro, dedicated carry logic, and IO blocks.

The icoBoard is pin compatible with the RaspberryPi 2B, newer versions, and any board using the same pin-out. The icoTC can generate bit stream files directly on the RaspberryPi.

As our tool targets small open source FPGAs and FPGA toolchains, we are simpler, more efficient, and easier to use.

Our open source FPGA toolchains can help you:

Offer products which are different from the products of your competitor

Offer more cost effective, easily available products

Present features others do not, and cannot provide

Our icoBoard is great for tinkerers, those who want to differentiate, test, and validate their product, and can be a huge enabler for creative technology in the future.

 

The icoBoard can also be operated standalone without RaspberryPi. Up to 200 IO Pins or 20 PMOD modules can be connected to the icoBOARD. 3 Flatflex connectors are available to connect additional boards.

For people already having an icoBoard_Beta, please see this page.

For people already having an icoBoard_Beta, please see icoBoard_beta

cropped-icoBoard.1.0_P1.P2.Pinout.jpg

Pin-out of P1 and P2 via icoBoard_beta

cropped-P3P4.png

Pin-out of P3 and P4 via icoBoard_beta

Existing Verilog open source projects

A lot of Verilog projects can be accessed and build via FuseSoC which also supports icoBoard
VHF Verilog SDR receiver written for Cyclone III
FM Radiosender in Verilog written for Cyclone III
H.264 Video encoder in VHDL

I2S

Radio Signal processing components are on github

Sump2 a FPGA based logic analyzer

icoSoC Risc-V Microcontroller with interfaces running on icoBoard

ridecore out-of-order Risc-V CPU

Zip CPU, a small CPU for FPGAs

manycore SoC components

USB Host 1.1 in Verilog

V-Scale Risc-V CPU implementation

multiplierless multiplication FFT and FIR Verilog Generator

complete 32 bit Risc-V SoC with lot of peripherals

Video pattern generation without Framebuffer (Video)

Ethernet Core, USB Core, PCIe core, SATA core

TCP/IP Stack for 10 GBit Ethernet

Ethernet Engine in Verilog

MMU Controller

a complete CPU with SPI, VGA, Serial

68000 CPU with gameconsole

SATA for Elphel Camera project

Bexkat1 32 bit CPU

DDR3 controller

SDRAM controller

AXI Bus open source implementation (SystemVerilog on Xilinx)

2D Graphics controller for Embedded MCU

Arcade emulator in FPGA and a video about it realised with Spartan3 and embedded ARM

Verilog code for SDR

Verilog Code for SDRAM controller

Verilog Code for another SDRAM controller (VHDL)

Some FPGA Project like PMODs with Verilog sourcecode (seems to be VHDL)

a GPS receiver implemented in Verilog

attaching a digital camera to PMODs
Infrared Receiver

Frequency counter

Digital Servo

6502 CPU Core (Verilog)

M32632 32bit CPU (Verilog)

I2S output (VHDL)

Floating Point Math in FPGA (VHDL generator)

Risc-V CPU (from Vectorblox)

GPU

Lots of complete legacy homecomputer systems implemented in Verilog like Acorn Archimedes

Infrared receiver

small gaming console with games on emulated CPU

A open source Verilog GPU implementation (will not fit into icoBoard) and  description

A small CPU with Debugger connection

Missing Verilog-blocks for icoBoard

DMA

Image Sensor Interface (DCMI Digital Camera Interface, CSI)

MMU

SDRAM

Flash controller

Floating Point Unit

CRC block

math block

data/audio/video stream/image compression/decompression block

Interrupt controller

Kalman filter

I2S

PWM

PID controller

high resolution rotary position decoder

BLDC controller

Random number generator

LCD Interface (DSI)

resistive touch interface

capacitive touch interface

PS/2 keyboard

PS/2 mouse

SSI/BiSS master interface device

Ethernet 10/100MBit

Timer

Counter

JESD204B interface

BiSS-C interface

multi device time synchronisation

AD converter (different speed and bitdepth)

DA converter (different speed and bitdepth)

Powerlink

EtherCAT

Flexray

SHA Engine

MD5 Engine

DES Engine

AES Engine

HW supported VPN for MCU

LIN

Most

LANc (Sony camera remote control)

one wire Battery management

narrow band digital signal filter

narrow band modulator/demodulator (FSK OOK QAM)

How about Xilinx, Altera and others?

We move forward as we have documentation about the chips available. There are huge differences in strategic interest of the chip manufacturers. We consider it currently very unlikely that Xilinx as the market leader will make available any chip documentation as NVidia still can afford to not make documentation available about its graphics chips.

Other FPGA chip companies might have different interests and the market is moving as Intel recently bought Altera and there are new contenders.

Clifford knows how to legally reverse engineer Xilinx chips (especially Series 7). Its just that it is a lot of boring work and Clifford is not interested in doing this work. If someone is willing to put in the effort, Clifford might help you out with some hints. But be prepared: you need to have serious knowledge in CS and EE.  Find some first hints here.