About icoBoard

Enabling open source FPGA solutions

icoBOARD is a FPGA based IO board for RaspberryPi. The icoBOARD contains a Lattice FPGA (Field Programmable Gate Array) with 8k LUT, 100MHz max clock, up to 8 MBit of SRAM and is programmable in Verilog (A hardware description language) by a complete open source FPGA toolchain.icoboard-vorne-1-1

The icoTC (toolchain consisting of Yosys and ArachnePnR and icetools) for the Lattice ICE40 series supports all chip components like PLLs, Block RAMs, the WARMBOOT macro, dedicated carry logic, and IO blocks.

The icoBoard is pin compatible with the RaspberryPi 2B, newer versions, and any board using the same pin-out. The icoTC can generate bit stream files directly on the RaspberryPi.

As our tool targets small open source FPGAs and FPGA toolchains, we are simpler, more efficient, and easier to use.

Our open source FPGA toolchains can help you:

Offer products which are different from the products of your competitor

Offer more cost effective, easily available products

Present features others do not, and cannot provide

Our icoBoard is great for tinkerers, those who want to differentiate, test, and validate their product, and can be a huge enabler for creative technology in the future.

 

The icoBoard can also be operated standalone without RaspberryPi. Up to 200 IO Pins or 20 PMOD modules can be connected to the icoBOARD. 3 Flatflex connectors are available to connect additional boards.

For people already having an icoBoard_Beta, please see this page.

For people already having an icoBoard_Beta, please see icoBoard_beta

cropped-icoBoard.1.0_P1.P2.Pinout.jpg

Pin-out of P1 and P2 via icoBoard_beta

cropped-P3P4.png

Pin-out of P3 and P4 via icoBoard_beta

GSoC Google Summer of Code

If you want to work within the Google Summer of Code program, you can find ideas we are interested in under the following links.

Fossi Foundation Yosys GSoC 2016

lowrisc Yosys GSoC 2016

 

The following list are general project ideas

  • Schematic Viewer for Netlists (SVG/JavaScript) Link

  • Porting ArachnePnR to OpenCL 1.2
  • Implementation Client of USB 2.0 of Daisho project  on icoBoard
  • Integrate FPGA tools like FuseSOC, Yosys, AachnePnR and a repository containing tested IP blocks into a webbased SOC generator suite for icoBoard and possible peripherals
  • implement a minion core executing a rump kernel in icoBoard acting as an device or network interface for the RaspberryPi (i2c,TCP/IP, i2s, SPI, CAN, PWM, Position, ..)
  • demo project tracking the position of a wireless microphone by radiosynchronized soundbeacons
  • implement a SDR narrowband modulator/demodulator in Verilog
  • implement a HDR video pipeline with a high speed low resolution camera sensor on icoBoard
  • implement a programmable smart powersupply with FPGA based control loops with icoTC
  • if you are an European Union citizen or from Asia of Africa: reverse and document a modern FPGA
  • Developing a Verilog Block listed here

Timeline

February 2015: Reverse engineering of Lattice ICE40 1k Chip

March 2015: reading of bitstream and conversion into Verilog

June 2015:  generation of Latice compatible bitstream by Yosis/ArachnePnR/ICEstorm

July: reverse engineering of Lattice ICE40 8k Chip

August 2015: porting of complete  toolchain to RaspberryPi, generation of bitstream and programming of Lattice ICE40 8k by RasPi

December 2015:  Presentation of complete solution and making available beta boards at 32C3 Hamburg

January 2016: Timing analysis done

February 2016:  SD support done, porting of micropython to icoBoard/Risc-V begins

June 2016: porting of Contiki OS to Risc-V is done

July 2016: 150 icoBoards have been manufactured and are distributed to developers

icoBoard 1.0

Attention! icoBoard 1.0 has a different pinout than the icoBoard beta. Find pinout below.

 

Get started with a Linux image and all required software HowTo

icoboard-vorne-1-1

icoBoard_1.0 is available in single quantity for a price of 90 Euro directly from stock plus taxes plus plus shipping (to Europe 10 Euro, everywhere else in the world 20 Euro).

icoboard-hinten-1-1

These icoBoards 1.1 do also have the option of up to 8MBit SRAM (could be used e.g. for a 8 bit 640*480 framebuffer), but those version will be 20 Euro more expensive.

icoBoards_1.0 are also available in packages of 20 pieces for a price of 70 Euro each and will be build to order once we have enough orders to order a production run of 100 pieces. To get the cheaper boards your waiting-time will depend on the overall demand. You can have any number of boards (as long as they are in stock) instantly for the price of 90 Euro.

If you are interested to order an even larger number of icoBoard_1.0, please get in contact with us.

If you have an icoBoard please join mailinglist

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Infos about icoBoard 1.0 (also called gamma )

The icoBoard_Beta is pin compatible with the RaspberryPI 2B and RaspberryPi B+ and all later revisions like the RaspberryPi 3. You can use the icoBoard 1.0 also with pincompatible boards like the OrangePi, but we did not test them. The icoBoard is not pin compatible with the original first RaspberryPi.

Please find the schematic here

Pinout Pmod P2 und P1

p1-p1

Pinout PMOD P3 und P4

p3p4

Pinout 4*17 100 mil connectors

A PDF version is available too.

layout-4_17

News

July 2016: 100 icoBoards1.0 have been manufactured are are available for purchase.

June 2016: We will present icoBoard at FPGA Kongress in Munich on 14th of July 2016

June 2016: icoBoard 1.0 is available now for 90 Euro

June 2016: We did port Contiki 2.0 to our Risc-V SoC running on the icoBoard

Feb 2016: BQ, the spanish mobilephone manufacturer, is building a Lattice based Arduinoboard using the icoTC.

icezum

Feb 2016: The first commercial product using the icoTC will be the Wiggleport

Feb 2016: Designwin. Olimex will manufacture FPGA Boards with Lattice FPGAs using icoTC.

Feb 2016: Silego Technologies as a manufacturer of programmable chips will work with us to support their chips in our toolchain.

Feb 2016: You want to work on a Verilog project during “Google Summer of Code” using Yosys and ArachnePnR? Get in contact with us.

Jan 2016: We will be at Embedded World in Nürnberg from 23-26 Feb

Jan 2016: We will be at Fosem 2016 in Brussels  Link

Jan 2016: Clifford managed to finalize the timing analysis for the FPGA:

Jan 2016: We are shipping out Beta boards to developers

icoboards

Dec 2015: Hackeraday features Clifford

Dec 2015: Clifford did his presentation at 32c3