The icoTC is currenlty available for Windows and Linux
Link to Windows version
High level Synthesis tools for FPGAs
MyHDL (Python HDL)
Verilog-to-RTL synthesis and formal verification
Verilog RTL Synthesis: Yosys
Place and Route for FPGAs
FPGA device programming
Lattice chip documentation and tools
By using Yosys as synthesis tool, you keep your Verilog project platform independent.
Arachne is currently not able to generate bitstreams for Xilinx or Altera devices. But you can use Yosys to do the synthesis and use the vendor PnR tools to generate valid bitstreams.