Timeline

February 2015: Reverse engineering of Lattice ICE40 1k Chip

March 2015: reading of bitstream and conversion into Verilog

June 2015:  generation of Latice compatible bitstream by Yosis/ArachnePnR/ICEstorm

July: reverse engineering of Lattice ICE40 8k Chip

August 2015: porting of complete  toolchain to RaspberryPi, generation of bitstream and programming of Lattice ICE40 8k by RasPi

December 2015:  Presentation of complete solution and making available beta boards at 32C3 Hamburg

January 2016: Timing analysis done

February 2016:  SD support done, porting of micropython to icoBoard/Risc-V begins

June 2016: porting of Contiki OS to Risc-V is done

July 2016: 150 icoBoards have been manufactured and are distributed to developers

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